Abstract
In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.
Funder
National Research Foundation of Korea (NRF) grant funded by the Korea government
National Research Foundation of Korea (NRF) through the Korea Government
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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