Investigation of Electro-Thermal Performance for TreeFET from the Perspective of Structure Parameters
-
Published:2023-03-24
Issue:7
Volume:12
Page:1529
-
ISSN:2079-9292
-
Container-title:Electronics
-
language:en
-
Short-container-title:Electronics
Author:
Liu Weijing1, Pan Xinfu1, Liu Jiangnan1, Li Qinghua2
Affiliation:
1. College of Electronics and Information Engineering, Shanghai University of Electric Power, Shanghai 200090, China 2. Radiawave Technologies Corporation Limited, Shenzhen 518172, China
Abstract
In this work, the electro-thermal properties of TreeFET, which combines vertically stacked nanosheet (NS) and fin-shaped interbridge (IB) channels, are investigated in terms of interbridge width (WIB), nanosheet space (SNS) and nanosheet width (WNS) by TCAD simulation. Electrical characteristics such as electron density distributions, on/off-state current (ION, IOFF), subthreshold swing (SS) and self-heating effects (SHE) such as lattice temperature and thermal resistance (Rth) are systematically studied to optimize the performance of TreeFET. The result shows that a smaller WIB mitigates the short-channel effects and increases the electron concentration in NS channels but increases thermal resistance. A larger SNS increases the on-state current while compensating for the gate drive loss and mitigating the thermal coupling effect between NS channels but results in longer conduction paths of carriers and heat, which hinders further improvements. Moreover, a suitable WNS is required to lessen the decline of gate controllability induced by IB channels. Hence, suitable geometry parameters should be selected to achieve a compromise between thermal and electrical performance.
Funder
National Natural Science Foundation of China
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference34 articles.
1. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm;Hisamoto;IEEE Trans. Electron Devices,2000 2. Vertical GAAFETs for the Ultimate CMOS Scaling;Yakimets;IEEE Trans. Electron Devices,2015 3. High-performance fully depleted silicon nanowire (diameter/spl les/5 nm) gate-all-around CMOS devices;Singh;IEEE Electron Device Lett.,2006 4. Weckx, P., Ryckaert, J., Litta, E.D., Yakimets, D., Matagne, P., Schuddinck, P., Jang, D., Chehab, B., Baert, R., and Gupta, M. (2019, January 7–11). Novel forksheet device architecture as ultimate logic scaling device towards 2 nm. Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 5. Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., and Demuynck, S. (2018, January 18–22). The Complementary FET (CFET) for CMOS scaling beyond N3. Proceedings of the 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA.
|
|