Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process

Abstract

This paper presents an integer-N phase-locked loop (PLL) for an RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback loop are proposed. The frequency range of the VCO is 4.5–6.1 GHz, the target frequency of the proposed PLL is 2.4 and 5.8 GHz in the industry–science–medical band. It is designed with a same phase margin and bandwidth using one loop filter. The proposed PLL consumes less than 8 mW from a 1.8 V power supply with a settling time of fewer than 20 μs and an area of 1200 μm × 800 μm in the 180 nm CMOS process. For a carrier frequency offset of 1 MHz, the measured phase noise is −118.5 dBc/Hz at 2.4 GHz and −116.6 dBc/Hz at 5.8 GHz. Its FoM including the phase noise is −197 dB at 2.4 GHz and −202.8 GHz at 5.8 GHz, outperforming other PLLs designed in the 180 nm CMOS process.