Author:
Zhang Xinyu,Du Qifei,Liu Cheng,Zhang Hao,Ma Yue,Li Yefei,Li Jinhuan
Abstract
The current work employs the HMC830 phase-locked loop chip to design a frequency synthesizer operating in the L-band. The frequency synthesizer can provide a local oscillation signal for the RF receiver front end. This article employs the phase-locked synthesis technique to describe the design scheme. Due to the advantages of the passive loop filters, such as simplicity, low cost, and low phase noise, a passive fourth-order RLC loop filter is proposed to improve the output signal quality and reduce phase noise. The performance of this loop filter is compared with the passive fourth-order RC loop filter. The effects of these two loop filters on phase noise, loop capture time, and spur suppression are analyzed. Subsequently, the design scheme, simulation analysis, and test results of the frequency synthesizer are presented under these two loop filters. The test results indicate that the passive fourth-order RLC loop filter outperforms the passive fourth-order RC loop filter; its output signal phase noise is higher than −100 dBc/Hz@1 kHz, loop capture time is less than 100 us, and spur suppression is better than 60 dBc. This frequency synthesizer can provide high-performance local oscillation signals for wireless communication equipment such as transmitters and receivers. It meets the application requirements of many radio communication circuit structures and has good application prospects.
Funder
National Natural Science Foundation of China
Youth Cross Team Scientific Research Project of the Chinese Academy of Sciences
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference28 articles.
1. An ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications;Bagheri;Int. J. Circuit Theory Appl.,2022
2. Abbas, W., Mehmood, Z., and Seo, M. (2020). A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS. Electronics, 9.
3. Frequency synthesis: Current status and future projections;Chenakin;Microw. J.,2017
4. Zhao, Y., Chen, Z., Liu, Z., Li, X., and Wang, X. (2020). A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer. Electronics, 9.
5. Yang, D.Y., Xu, J., and Du, H. (2020, January 20–23). A High Performance Frequency Synthesis Method Based on PLL and DDS. Proceedings of the13th International Conference on Microwave and Millimeter Wave Technology (ICMMT), Electr Network, Shanghai, China.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献