Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits-Reference-Cited by-同舟云学术

Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

Published:2023-11-11 Issue:22 Volume:12 Page:4615
ISSN:2079-9292
Container-title:Electronics
language:en
Short-container-title:Electronics

Author:

Maljar David¹^ORCID,Sovcik Michal¹^ORCID,Potocny Miroslav¹^ORCID,Ondica Robert¹^ORCID,Arbet Daniel¹^ORCID,Stopjakova Viera¹^ORCID

Affiliation:

1. Department of IC Design and Test, Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Ilkovicova 3, 841 04 Bratislava, Slovakia

Abstract

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage VIN_OFF of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the VIN_OFF of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage VDD = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations.

Funder

Slovak Research and Development Agency

the Ministry of Education, Science, Research and Sport of the Slovak Republic

Electronic Components and Systems for European Leadership Joint Undertaking

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Link

https://www.mdpi.com/2079-9292/12/22/4615/pdf

Reference37 articles.

1. Razavi, B. (2000). Design of Analog CMOS Integrated Circuits, McGraw-Hill Education. [2nd ed.].

2. Schaper, U., and Linnenbank, C. (2003, January 16–18). Comparison of Distance Mismatch and Pair Matching of CMOS Devices. Proceedings of the ESSCIRC 2004—29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), Estoril, Portugal.

3. Process Variation and Pelgrom’s Law [Circuit Intuitions];Sheikholeslami;IEEE J. Solid-State Circuits,2015

4. Matching properties of MOS transistors;Pelgrom;IEEE J. Solid-State Circuits,1989

5. Characterisation and modeling of mismatch in MOS transistors for precision analog design;Lakshmikumar;IEEE J. Solid-State Circuits,1986