SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect-Reference-Cited by-同舟云学术

SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect

Published:2024-04-28 Issue:9 Volume:13 Page:1701
ISSN:2079-9292
Container-title:Electronics
language:en
Short-container-title:Electronics

Author:

Sang Ling¹²,Jin Rui¹²,Cui Jiawei³^ORCID,Niu Xiping¹²,Li Zheyang¹²,Yang Junjie³,Nuo Muqin³,Zhang Meng⁴,Wang Maojun³,Wei Jin³

Affiliation:

1. Beijing Institute of Smart Energy, Beijing 102209, China

2. Beijing Huairou Laboratory, Beijing 101409, China

3. The School of Integrated Circuits, Peking University, Beijing 100871, China

4. The College of Microelectronics, Beijing University of Technology, Beijing 100124, China

Abstract

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.

Publisher

MDPI AG

Link

https://www.mdpi.com/2079-9292/13/9/1701/pdf

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