A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications
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Published:2023-07-24
Issue:14
Volume:12
Page:3196
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Jiang Yingdan12, Yu Yang2, Tang Lu3ORCID, Yang Junhao2, Lu Yujia3, Yu Zongguang12
Affiliation:
1. School of Electronic Science and Engineering, Nanjing University, Nanjing 210093, China 2. The 58th Research Institute of China Electronic Technology Group Corporation, Wuxi 214072, China 3. Engineering Research Centre of RF-ICs & RF-Systems, Ministry of Education, Southeast University, Nanjing 210096, China
Abstract
This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.
Funder
Natural Science Foundation of Jiangsu Province National Natural Science Foundation of China
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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