A 68.6fs<sub>rms</sub>-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching-Reference-Cited by-同舟云学术

A 68.6fs_rms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching

Published:2022-02-20 Issue: Volume: Page:
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Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Dartizio Simone Mattia¹,Buccoleri Francesco¹,Tesolin Francesco¹,Avallone Luca²,Santiccioli Alessio¹,Iesurum Agata³,Steffan Giovanni²,Cherniak Dmytro²,Bertulessi Luca¹,Bevilacqua Andrea³,Samori Carlo¹,Lacaita Andrea Leonardo¹,Levantino Salvatore¹

Affiliation:

1. Politecnico di Milano,Milan,Italy

2. Infineon Technoloaies,Villach,Austria

3. University of Padova,Padova,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731683.pdf?arnumber=9731683

Reference5 articles.

1. A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range

2. A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

3. Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

4. A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

5. A 66fsrms Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking;santiccioli;ISSCC,2020

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