Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors

Author:

Stampfer BernhardORCID,Schanovsky Franz,Grasser Tibor,Waltl MichaelORCID

Abstract

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Extraction of Charge Trapping Kinetics of Defects From Single-Defect Measurements;IEEE Transactions on Device and Materials Reliability;2024-06

2. Advanced Extraction of Trap Parameters from Single-Defect Measurements;2023 IEEE International Integrated Reliability Workshop (IIRW);2023-10-08

3. Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO2Transistors;IEEE Transactions on Device and Materials Reliability;2023-09

4. Evaluation of the impact of defects on threshold voltage drift employing SiO2 pMOS transistors;Microelectronics Reliability;2022-11

5. Impact of Single Defects on NBTI and PBTI Recovery in SiO2 Transistors;2022 IEEE International Integrated Reliability Workshop (IIRW);2022-10-09

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