Affiliation:
1. Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2. University of Chinese Academy of Sciences, Beijing 100049, China
Abstract
This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.
Funder
Key Research and Development Plan of Shandong Province, China
Youth Innovation Promotion Association, Chinese Academy of Sciences
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference20 articles.
1. A 4-GS/s single channel reconfigurable folding flash ADC for wireline applications in 16-nm FinFET;Wang;IEEE Trans. Circuits Syst. II Express Briefs,2017
2. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration;Ali;IEEE J. Solid-State Circuits,2014
3. Ali, A.M., Dinc, H., Bhoraskar, P., Puckett, S., Morgan, A., Zhu, N., and Taylor, G. (2016, January 15–17). A 14-bit 2.5 GS/s and 5 GS/s RF sampling ADC with background calibration and dither. Proceedings of the 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, USA.
4. A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm 2 and 500 mW in 40 nm Digital CMOS;Chen;IEEE J. Solid-State Circuits,2012
5. A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology;Devarajan;IEEE J. Solid-State Circuits,2017