A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither-Reference-Cited by-同舟云学术

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A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

Published:2016-06 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
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Author:

Ali Ahmed M.A.,Dinc Huseyin,Bhoraskar Paritosh,Puckett Scott,Morgan Andy,Ning Zhu ,Qicheng Yu ,Dillon Chris,Gray Bryce,Lanford Jon,McShea Matt,Mehta Ushma,Bardsley Scott,Derounian Peter,Bunch Ryan,Moore Ralph,Taylor Gerry

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7569797/7573453/07573537.pdf?arnumber=7573537

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06

2. Digital Background Calibration Techniques for Interstage Gain Error and Nonlinearity in Pipelined ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

4. A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

5. A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor;IEEE Journal of Solid-State Circuits;2023-12

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