Author:
Saha Aloke,Singh Narendra Deo
Subject
Mechanical Engineering,Condensed Matter Physics,General Materials Science
Cited by
6 articles.
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1. Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass Transistor Logic;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06
2. Performance Analysis of Ternary Full Adder designs using proposed Ternary 3:1 MUX;2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON);2023-08-23
3. Novel 32nm CMOS Ternary 3‘s Complement Generator;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07
4. Novel 32nm CMOS Ternary Parity Generator-Checker;2022 International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON);2022-11-11
5. Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier;Microelectronics Journal;2022-01