Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier-Reference-Cited by-同舟云学术

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Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier

Published:2022-01 Issue: Volume:119 Page:105318
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Saha Aloke^ORCID,Singh Rakesh Kumar^ORCID,Pal Dipankar^ORCID

Publisher

Elsevier BV

Subject

General Engineering

Reference34 articles.

1. Systematic synthesis of approximate adders and multipliers with accurate error calculations;Nojehdeh;Integrat. VLSI J.,2020

2. A novel method for reduction partial product tree in ternary multiplier;Tabrizchi;Microelectron. J.,2020

3. Design and analysis of approximate redundant binary multipliers;Liu;IEEE Trans. Comput.,2019

4. Implementation of energy-efficient approximate multiplier with guaranteed worst case relative error;Loukrakpamand;Microelectron. J.,2019

5. Design and analysis of multiplier using approximate 4-2 compressor;Reddy;AEU-Int. J. Electr. Commun.,2019

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2. Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications;Analog Integrated Circuits and Signal Processing;2024-02-09

3. Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder;IETE Journal of Research;2023-10-16

4. Design of Area-speed Efficient Anurupyena Vedic Multiplier for Deep Learning Applications;2023-07-27

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