The Interaction Challenges with Novel Materials in Developing High-Performance and Low-Leakage High-k/Metal Gate CMOS Transistors

Author:

Chudzik Michael,Krishnan Siddarth,Kwon Unoh,Khare Mukesh,Narayanan Vijay,Ando Takashi,Cartier Ed,Bu Huiming,Paruchuri Vamsi

Publisher

Wiley-VCH Verlag GmbH & Co. KGaA

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4. Mistry , K. Allen , C. Auth , C. Beattie , B. Bergstrom , D. Bost , M. Brazier , M. Buehler , M. Cappellani , A. Chau , R. Choi , C.-H. Ding , G. Fischer , K. Ghani , T. Grover , R. Han , W. Hanken , D. Hattendorf , M. He , J. Hicks , J. Huessner , R. Ingerly , D. Jain , P. James , R. Jong , L. Joshi , S. Kenyon , C. Kuhn , K. Lee , K. Liu , H. Maiz , J. Mclntyre , B. Moon , P. Neirynck , J. Pae , S. Parker , C. Parsons , D. Prasad , C. Pipes , L. Prince , M. Ranade , P. Reynolds , T. Sandford , J. Shifren , L. Sebastian , J. Seiple , J. Simon , D. Sivakumar , S. Smith , P. Thomas , C. Troeger , T. Vandervoorn , P. Williams , S. Zawadzki , K. 2007 A 45 nm logic technology with high-κ/metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging 247

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