Packaging Parameters Analysis for the Fatigue Reliability of Stacked Chip Ball Grid Array by Using the Optimal Equivalent Solder Balls
Author:
Affiliation:
1. Department of Engineering Science; National Cheng Kung University; 701 Tainan City Taiwan
2. Technical Development Department; NXP Semiconductors Taiwan; 811 Kaohsiung City Taiwan
Publisher
Wiley
Subject
Management Science and Operations Research,Safety, Risk, Reliability and Quality
Link
http://onlinelibrary.wiley.com/wol1/doi/10.1002/qre.1611/fullpdf
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3. Reliability-based design optimization of computation-intensive models making use of response surface models;Steenackers;Quality and Reliability Engineering International,2011
4. Robust design via simulation experiments: a modified dual response surface approach;Giovagnoli;Quality and Reliability Engineering International,2008
5. Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages;Tee;Journal of Microelectronic Reliability,2004
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1. Interval optimal design of 3-D TSV stacked chips package reliability by using the genetic algorithm method;Microelectronics Reliability;2014-12
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