Advanced Embedded Trace Substrate – A Flexible Alternative to Fan‐Out Wafer Level Packaging-Reference-Cited by-同舟云学术

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Advanced Embedded Trace Substrate – A Flexible Alternative to Fan‐Out Wafer Level Packaging

Published:2021-12-03 Issue: Volume: Page:217-231
ISSN:
Container-title:Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces
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Author:

Hsu Shih Ping,Hsu Byron,Chou Adan

Publisher

Wiley

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/9781119793908.ch9

Reference5 articles.

1. Chen E. You J. Lan A. andLiao M.(2014).Structure reliability and characterization for FC package w/Embedded Trace coreless Substrate.Proceedings of the 16th Electronics Packaging Technology Conference (EPTC). IEEE.

2. Tang T. Lan A. Tsai J. Lin S. Ho D. andYou J.(2015).Challenges of flip chip packaging with embedded fine line and multi‐layer coreless substrate.Proceedings of the 65th Electronic Components and Technology Conference (ECTC). IEEE.

3. Hsieh M. Cho N.andKang K.(2017).Development of thin flip chip package with low cost substrate technology.Proceedings of the 12th International Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT). IEEE.

4. Wei C.C. Yu C.H. Tung C.H.et al. (2011).Comparison of the electromigration behaviors between micro‐bumps and C4 solder bumps.Proceedings of the 61st Electronic Components and Technology Conference (ECTC). IEEE.

5. LwinK.K. Tubillo C.E. Panumard T.J.D.et al. (2016).Copper Clip Package for high performance MOSFETs and its optimization.Proceedings of the 18th Electronics Packaging Technology Conference. IEEE.

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1. Design and Simulation Study of 300-GHz Molded Patch Antenna in Packaging Substrate;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

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