1. Intel enters the third dimension;Cartwright;Nature,2011
2. Nanoscale channel engineered double gate MOSFET for mixed signal applications using high-k dielectric;Nirmal;International Journal of Circuit Theory and Applications,2013
3. Lee H et al Negative bias temperature instability in SOI and body-tied double-gate FinFETs Symposium on VLSI Technology Digest 2005 110 111
4. Zafar S et al A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates . IEEE Symposium on VLSI Technology. Digest of Technical Papers, 2006 23 25
5. International Technology Roadmap for Semiconductors 2013 http://www.itrs.net/Links/2013ITRS/Home2013.htm