System level design and analysis of a fourth-order continuous-time delta-sigma modulator using relaxed gain-band-width amplifiers

Author:

Hasanzadeh Mohammad Reza1,Abrishamifar Adib2

Affiliation:

1. School of Electrical Engineering; Iran University of Science and Technology; Tehran Iran

2. Microelectronics Laboratory, School of Electrical Engineering; Iran University of Science and Technology; Tehran Iran

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference23 articles.

1. A 20 mW 640-MHz CMOS continuous-time ΣΔ_ ADC with 20 MHz signal bandwidth,80-dB dynamic range and 12-bit ENOB;Mitteregger;IEEE Journal of Solid-State Circuits,2006

2. Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter;Reddy;IEEE Transactions on Circuits and Systems I: Regular Papers,2007

3. Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass ΔΣ modulator;Shoaei;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,1997

4. Design of continuous-time sigma-delta modulators with arbitrary feedback waveform;Oliaei;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,2003

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Quantization noise upconversion effects in mixer‐first direct delta‐sigma receivers;International Journal of Circuit Theory and Applications;2019-11-03

2. A 20-MHz bandwidth, 75-dB dynamic range, continuous-time delta-sigma modulator with reduced nonidealities;International Journal of Circuit Theory and Applications;2019-06-25

3. A novel OTA compensation approach suitable for CT-ΔΣ modulators;International Journal of Circuit Theory and Applications;2018-07-04

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