Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter-Reference-Cited by-同舟云学术

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Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

Published:2007-10 Issue:10 Volume:54 Page:2184-2194
ISSN:1057-7122
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Reddy Karthikeyan,Pavan Shanthi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/4346657/04346678.pdf?arnumber=4346678

Cited by 58 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of Random Clock Jitter Effect in Time-Interleaved DACs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing;IEEE Open Journal of Circuits and Systems;2024

3. A high-dynamic-range digital RF-over-fiber link for MRI receive coils using delta–sigma modulation;Review of Scientific Instruments;2021-06-01

4. A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver;IEEE Journal of Solid-State Circuits;2021-05

5. A Second-Order Purely VCO-Based CT $\Delta\Sigma$ ADC Using a Modified DPLL Structure in 40-nm CMOS;IEEE Journal of Solid-State Circuits;2020-02

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