On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm-Reference-Cited by-同舟云学术

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On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm

Published:2019-08-13 Issue:23 Volume:32 Page:
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat Pract Exper

Author:

Shang Qianyi¹,Chen Lijun¹^ORCID,Peng Peng²

Affiliation:

1. Equipment Simulation Training Center Army Engineering University of PLA Nanjing China

2. Department of Teaching and Research Army Engineering University of PLA Nanjing China

Funder

National Natural Science Foundation of China

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.5486

Reference30 articles.

1. Complete hardware evolution based SoPC for evolvable hardware

2. SalvadorR.Evolvable hardware in FPGAs: embedded tutorial. In: Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS);2016;Istanbul Turkey.

3. Introduction to Evolutionary Computing

4. KalganovaT.An extrinsic function‐level evolvable hardware approach. In: Proceedings of the 3th European Conference on Genetic Programming (EuroGP2000);2000;Edinburgh UK.

5. An evolved circuit, intrinsic in silicon, entwined with physics

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