Low power and area efficient error tolerant adder for image processing application

Author:

Priyadharshni M1,Kumaravel Sundaram1ORCID

Affiliation:

1. Department of Micro and Nano electronics, School of Electronics EngineeringVellore Institute of Techonology Vellore India

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. APPAs: fast and efficient approximate parallel prefix adders and multipliers;The Journal of Supercomputing;2024-07-24

2. Energy Efficient 2D FIR Filter and Multiplier Design for Image Processing Applications;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

3. Hybrid image compression algorithm based on wavelet transform and number theoretic transformation;International Journal of Circuit Theory and Applications;2024-06-12

4. Carry Select Adder Using Square Root Techniques in Ripple Carry and BCD Adders;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06

5. Efficient and low-cost approximate multipliers for image processing applications;Integration;2024-01

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