P‐21: Post‐Annealing Optimization for Top‐Gate Amorphous In‐Ga‐Zn‐O Thin‐Film Transistors with Atomic‐Layer‐Deposited Ultrathin AlO<sub>x</sub> Dielectric-Reference-Cited by-同舟云学术

P‐21: Post‐Annealing Optimization for Top‐Gate Amorphous In‐Ga‐Zn‐O Thin‐Film Transistors with Atomic‐Layer‐Deposited Ultrathin AlO_x Dielectric

Published:2024-06 Issue:1 Volume:55 Page:1438-1440
ISSN:0097-966X
Container-title:SID Symposium Digest of Technical Papers
language:en
Short-container-title:Symp Digest of Tech Papers

Author:

Li Jiye¹,Yang Huan¹,Li Xiao¹,Zhang Yuqing²,Wang Xinwei³,Lu Lei¹,Zhang Shengdong¹

Affiliation:

1. School of Electronic and Computer Engineering Peking University Shenzhen China

2. Department of Electronic and Computer Engineering Hong Kong University of Science and Technology China Hong Kong

3. School of Advanced Materials Peking University Shenzhen China

Abstract

The effects of post‐annealing on amorphous InGaZnO (a‐IGZO) TFTs with ultrathin atomic layer deposited (ALD) AlOxgate insulator (GI) were investigated. The non‐annealed devices exhibited uncontrollable gate leakage current while postannealing in either oxygen (O2) or nitrogen (N2) exhibited noticeable improvements. Optimizing O2‐annealed devices demonstrated the most optimal performance, including a low subthreshold swing of 61.6 mV/dec and a high on/off current ratio over 109. Capacitance‐voltage and X‐ray photoelectron spectroscopy analyses further revealed the underlying mechanism of defect elimination at the AlOx/a‐IGZO interface.

Publisher

Wiley

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