A fast pull-in PLL IC using two-mode pull-in technique

Author:

Sato Hideo,Kato Kazuo,Sase Takashi,Ikushima Ichiro,Kojima Shin-ichi

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference13 articles.

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4. et al. A monolithic 50-200 MHz CMOS clock recovery and retiming circuit. Proc., CICC, pp. 1451–1454 (May 1989).

5. A 50 MHz phase- and frequency-locked loop

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