Affiliation:
1. National Key Laboratory of Science and Technology on Communication University of Electronic Science and Technology of China Chengdu Sichuan China
2. Research Institute of Electronic Science and Technology University of Electronic Science and Technology of China Chengdu Sichuan China
3. Department of Computer Engineering Persian Gulf University Bushehr Iran
Abstract
AbstractThe advent of Network Function Virtualization (NFV) technology brings flexible traffic engineering to edge computing environments. Online services in NFV are chained as Service Function Chains (SFCs), which consist of ordered sequences of Virtual Network Functions (VNFs). The SFC Placement (SFCP) problem is solved under Quality of Service (QoS) requirements and limited resource availability by directing traffic to the required VNFs. However, SFC assembly leads to high latency and network congestion by increasing the count of VNFs, which parallelized SFC can overcome this problem. With parallelizing an SFC request, independent VNFs are activated simultaneously and computational acceleration is realized by reducing the SFC length. Any pair of VNFs that do not conflict with traffic can be activated simultaneously. Most VNFs are deployed on distributed servers for load balancing, which makes SFC parallelization challenging. Meanwhile, the cost of merging/duplicating packets for parallelized SFCs between different servers is not negligible. Hence, in this article, Distributed Parallel Chaining (DPC) is proposed which is an algorithm based on Deep Reinforcement Learning (DRL) approaches. The DPC algorithm solves the SFCP problem to maximize the Long‐Term Expected Cumulative Reward (LTECR). DPC incorporates an Asynchronous Advantage Actor‐Critic (A3C) algorithm as a new approach based on DRL to increase the admission ability of future SFC requests by maximizing LTECR. The evaluation results show the effectiveness of the proposed algorithm from different aspects. Specifically, compared to the best existing approaches, DPC can reduce SFC latency by 8.7%.
Subject
Electrical and Electronic Engineering
Cited by
3 articles.
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