Tamper Resistance Simulation on Algorithm Level Design

Author:

Yoshikawa Masaya12,Asai Toshiya12,Shiozaki Mitsuru23,Fujino Takeshi23

Affiliation:

1. Meijo University; Japan

2. JST, CREST; Japan

3. Ritsumeikan University; Japan

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Energy Engineering and Power Technology

Reference26 articles.

1. Kocher PC Jaffe J Jun B Differential power analysis 388 397

2. Algorithm level evaluation of DPA resistivity against cryptosystems;Sasaki;IEEJ Trans EIS,2006

3. Miyamoto A Homma N Aoki T Satoh A An experimental comparison of power analysis attacks against RSA processors on ASIC and FPGA 53 63 2009

4. Kojima K Okuyama K Iwai K Shiozaki M Yoshikawa M Fujino T LSI implementation method of DES cryptographic circuit utilizing domino-RSL gate resistant to DPA attack 169 201 2010

5. Correlation power analysis with a leakage model;Brier;Proc of Cryptographic Hardware and Embedded Systems,2004

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