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On the simulation of fast settling charge pump PLLs up to fourth order

  • Published:2010-06-11 Issue:12 Volume:39 Page:1257-1273
  • ISSN:0098-9886
  • Container-title:International Journal of Circuit Theory and Applications
  • language:en
  • Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Guermandi Marco,Franchi Eleonora,Gnudi Antonio

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications;Ahn;IEEE Journal of Solid-State Circuits,2000

2. A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation;von Kaenel;IEEE Journal of Solid-State Circuits,1996

3. A current-mode 1 kHz/10 kHz low-voltage integrated analogue PLL for lock-in portable applications;Ferri;International Journal of Circuit Theory and Applications,2003

4. A fully integrated CMOS DCS-1800 frequency synthesizer;Craninckx;IEEE Journal of Solid-State Circuits,1998

5. A 1-V 5.2-GHz CMOS synthesizer for WLAN applications;Leung;IEEE Journal of Solid-State Circuits,2004

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2. Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications;International Journal of Circuit Theory and Applications;2018-12-10

3. Systematic analysis and design of dual-switch Flyback converter;Journal of the Chinese Institute of Engineers;2015-11-05

4. A wideband low-spur 0.18-µm CMOS phase-locked loop with bandwidth calibration;International Journal of Circuit Theory and Applications;2015-05-06

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