RNS processor using moduli sets of the form 2n±1

Abstract

SummaryIn recent years, research on residue number systems (RNS) has targeted larger dynamic ranges to explore their inherent parallelism further. In this paper, we start from the traditional 3‐moduli set , with an equivalent 3 ‐bit dynamic range, and propose balanced horizontal extensions by using modulus of the form and to scale the dynamic range and enhance the parallelism according to the requirements. A method to design the reverse conversion by using it is also presented. A case study of multiplier‐accumulator (MACs) in cascade for filtering applications has been analyzed to validate the RNS processor using the proposed moduli set and reverse conversion architecture. Experimental results show that the proposed approaches achieve a significant speedup compared with the state‐of‐the‐art cases for the same dynamic range purposes.