Parallel execution on the function-partitioned processor with multiple instruction streams

Author:

Sowa Masahiro,Arita Takaya,Kawamura Tadaaki,Takagi Hiromitsu

Publisher

Wiley

Subject

Computational Theory and Mathematics,Hardware and Architecture,Information Systems,Theoretical Computer Science

Reference8 articles.

1. M. Sowa. A proposal for PN computer. Proc. Comp. Arch. Symp., Inf. Proc. Soc., Japan, pp. 109–114 (1988).

2. J. A. Fisher. Very long instruction word architecture and the ELI-512. Proc. of 10th International Symposium on Computer Architecture, pp. 140–150 (1983).

3. Dynamic microprogrammable computer with low-level parallelism;Hagiwara;IEEE Trans. Comput.,1980

4. Decoupled Access/Execute Computer Architectures;Smith;ACM Trans. Computer Systems,1984

5. M. Sowa. A control flow parallel computer architecture. Tech. Rep. Comp. Arch., Inf. Proc. Soc., Japan, 48–2 (1983).

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