Contact‐Engineering of Self‐Aligned‐Gate Metal Oxide Transistors Processed via Electrode Self‐Delamination and Rapid Photonic Curing

Author:

Luo Linqu1,Faber Hendrik1,Liu Chen2,Doukas Spyros3,Yarali Emre1,Adilbekova Begimai1,Naphade Dipti R.1,Xiao Na4,Ma Yinchang2,Mazo‐Mantilla Harold F.1,Panagiotidis Lazaros1,Alghamdi Wejdan S.1,Florica Camelia Florina5,Nugraha Mohamad Insan1,Li Xiaohang4,Zhang Xixiang2,Heeney Martin1,Lidorikis Elefterios3,Anthopoulos Thomas D.16ORCID

Affiliation:

1. KAUST Solar Center (KSC) King Abdullah University of Science and Technology (KAUST) Thuwal 23955‐6900 Saudi Arabia

2. Physical Science and Engineering Division King Abdullah University of Science and Technology (KAUST) Thuwal 23955‐6900 Saudi Arabia

3. Department of Materials Science and Engineering University of Ioannina Ioannina 45110 Greece

4. Computer, Electrical and Mathematical Science and Engineering Division King Abdullah University of Science and Technology (KAUST) Thuwal 23955‐6900 Saudi Arabia

5. Nanofabrication Core Lab King Abdullah University of Science and Technology (KAUST) Thuwal 23955‐6900 Saudi Arabia

6. Henry Royce Institute and Photon Science Institute Department of Electrical and Electronic Engineering The University of Manchester Oxford Road Manchester M13 9PL UK

Abstract

AbstractMetal oxide thin‐film transistors (TFTs) offer remarkable opportunities for applications in emerging transparent and flexible microelectronics. Unfortunately, their performance is hindered by limitations associated with parasitic effects, such as parasitic electrode overlap capacitances and high contact resistance, which can severely limit their dynamic behavior. Here, an innovative method is reported to fabricate coplanar self‐aligned‐gate (SAG) indium‐gallium‐zinc‐oxide (IGZO) transistors with engineered source/drain contacts. The manufacturing process starts with the deposition and patterning of a gate electrode/dielectric stack and its functionalization with an organic self‐assembled monolayer (SAM) as the surface energy modifier. A second gold (Au) electrode is subsequently deposited over the gate electrode stack. The overlapping region between the two electrodes is removed via self‐delamination under mild sonication, forming perfectly aligned coplanar Au‐Gate‐Au electrodes. Device fabrication is completed with the spin coating of the IGZO precursor, followed by rapid photonic curing. Replacing the gold source/drain contact with bimetallic electrodes such as Au/In and Au/ITO enables a reduction in contact resistance and improves the transistor performance remarkably without increasing manufacturing complexity. The method is highly scalable, robust, and applicable to other semiconductor materials.

Funder

Global Collaborative Research, King Abdullah University of Science and Technology

Publisher

Wiley

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