Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX-Reference-Cited by-同舟云学术

Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX

Published:2021-08 Issue: Volume: Page:
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat Pract Exper

Author:

Alappat Christie¹^ORCID,Meyer Nils²,Laukemann Jan¹,Gruber Thomas¹,Hager Georg¹^ORCID,Wellein Gerhard¹,Wettig Tilo²

Affiliation:

1. Erlangen National High Performance Computing Center Friedrich‐Alexander‐Universität Erlangen‐Nürnberg Erlangen Germany

2. Department of Physics University of Regensburg Regensburg Germany

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.6512

Reference37 articles.

1. AlappatC LaukemannJ GruberT et al. Performance Modeling of Streaming Kernels and Sparse Matrix‐Vector Multiplication on A64FX. Paper presented at: Proceedings of the 2020 IEEE/ACM Performance Modeling Benchmarking and Simulation of High Performance Computer Systems (PMBS) Atlanta GA USA; November 12 2020:1‐7; IEEE.https://doi.org/10.1109/PMBS51919.2020.00006

2. ARM C Language Extensions for SVE.https://developer.arm.com/documentation/100987/0000/. Accessed September 28 2020.

3. HofmannJ.ibench – Measure Instruction Latency and Throughput;2018.https://github.com/RRZE‐HPC/ibench.

4. Fujitsu LimitedA64FX Microarchitecture Manual 1.3. Fujitsu Limited;2020.https://github.com/fujitsu/A64FX/blob/1b3071af0369ee02b1752b7556e949050349985d/doc/A64FX_Microarchitecture_Manual_en_1.3.pdf.

5. TreibigJ HagerG WelleinG. LIKWID: A Lightweight Performance‐Oriented Tool Suite for x86 Multicore Environments. Paper presented at: Proceedings of the 2010 39th International Conference on Parallel Processing Workshops San Diego GA USA; September 13 2010:207‐216; IEEE.https://doi.org/10.1109/ICPPW.2010.38

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