The impact of interface and border traps on current-voltage, capacitance-voltage, and split-CV mobility measurements in InGaAs MOSFETs-Reference-Cited by-同舟云学术

The impact of interface and border traps on current-voltage, capacitance-voltage, and split-CV mobility measurements in InGaAs MOSFETs

Published:2016-11-15 Issue:3 Volume:214 Page:1600592
ISSN:1862-6300
Container-title:physica status solidi (a)
language:en
Short-container-title:Phys. Status Solidi A

Author:

Pavan Paolo¹,Zagni Nicolò¹,Puglisi Francesco Maria¹,Alian Alireza²,Thean Aaron Voon-Yew²,Collaert Nadine²,Verzellesi Giovanni³

Affiliation:

1. Dipartimento di Ingegneria “Enzo Ferrari” (DIEF); University of Modena and Reggio Emilia; via Vivarelli 10 41125 Modena Italy

2. imec; Kapeldreef 75 3001 Leuven Belgium

3. Dipartimento di Scienze e Metodi dell'Ingegneria (DISMI); University of Modena and Reggio Emilia; via Amendola 2 42122 Reggio Emilia Italy

Publisher

Wiley

Subject

Materials Chemistry,Electrical and Electronic Engineering,Surfaces, Coatings and Films,Surfaces and Interfaces,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference18 articles.

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2. Interface-Trap Effects in Inversion-Type Enhancement-Mode $\hbox{InGaAs/ZrO}_{2}$ N-Channel MOSFETs

3. M. J. W. Rodwell U. Singisetti M. Wisteky G. J. Burek A. Carter A. Baraskar J. Law B. J. Thibeault E. J. Kim B. Shin Y-J. Lee S. Steiger S. Lee H. Ryu Y. Tan G. Hegde L. Wang E. Chagarov A. C. Gossard W. Frensley A. Kummel C. Palmstrøm P. C. McIntyre T. Boykin G. Klimek P. Asbeck 25 30 2010

4. Charge accumulation and mobility in thin dielectric MOS transistors

5. Errors Limiting Split-$CV$ Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs

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