Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects
Author:
Affiliation:
1. Advanced Memory Development CenterToshiba Memory Corporation, Yamanoisshiki‐cho Yokkaichi Japan
2. Graduate School of EngineeringNagoya University, Furo‐cho Chikusa Nagoya Japan
Publisher
Wiley
Subject
Polymers and Plastics,Condensed Matter Physics
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/ppap.201900039
Reference171 articles.
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