A Deep Learning Model for Wafer Defect Map Classification: Perspective on Classification Performance and Computational Volume

Abstract

Wafer defect map images are generated by performing electrical tests on each chip on wafer. These images demonstrate specific failure patterns occurred from semiconductor manufacturing process. It is crucial for engineers to classify what kind of defect patterns on this wafer is early. In an attempt to automate the classification of wafer defect maps, which are currently manual dependent, various machine learning and deep learning models have been introduced. However, it has not been successfully applied to real‐world mass production environments due to problems such as classification performance and computational volume. Therefore, the deep learning model integrating the Inception module and the skip connection module for wafer defect map classification is proposed here. This model has a fast training and inference speed with a small number of parameters, it is highly practical when processing large amounts of real‐time test data in a semiconductor manufacturing environment because of its small computational volume and high classification performance. This method is applied on the real‐field wafer test data, and the result shows that the proposed model takes a significant improvement on inference time by over 59% with high performance compared to the baseline model.