A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes

Author:

Sharma Vishal1,Vishvakarma Santosh1ORCID,Chouhan Shailesh Singh2,Halonen Kari3

Affiliation:

1. Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering; Indian Institute of Technology; Indore India

2. EISLAB, Department of Computer Science, Electrical and Space Engineering; Lulea University of Technology; Lulea Sweden

3. Electronic Circuit Design Lab, Department of Electronics and Nano Engineering; Aalto University; Espoo Finland

Funder

Center for International Mobility (CIMO)

Aalto University, Finland

Special Manpower Development Program for Chips to System Design (SMDP-C2SD)

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference27 articles.

1. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks;Chen;IEEE J Solid-State Circuits,2017

2. An Early Resource Characterization of Deep Learning on Wearables, Smartphones and Internet-of-Things Devices

3. Design of low-power CMOS cell structures using subthreshold conduction region;Sharma;Int J Sci Eng Res,2011

4. 40 nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist;Chiu;IEEE Trans Circuits Syst I: Regul Pap,2014

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