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An efficient method for reconfiguring power-efficient VLSI array with maximum satisfiability

  • Published:2018-02-06 Issue:5 Volume:13 Page:770-776
  • ISSN:1931-4973
  • Container-title:IEEJ Transactions on Electrical and Electronic Engineering
  • language:en
  • Short-container-title:IEEJ Trans Elec Electron Eng

Author:

Qian Junyan1,Chen Cong1,Zhao Lingzhong1,Guo Yunchuan2

Affiliation:

1. Guangxi Key Laboratory of Trusted Software; Guilin University of Electronic Technology; Guilin 541004 China

2. State Key Laboratory of Information Security, Institute of Information Engineering; Chinese Academy of Sciences; Beijing 100093 China

Funder

National Natural Science Foundation of China

High Level Innovation Team of Guangxi Colleges and Universities and Outstanding Scholars Fund

Guangxi Natural Science Foundation of China

GUET Graduate Education

Guangxi Key Laboratory of Trusted Software Focus Fund

Guilin University of Electronic Technology

Publisher

Wiley

Subject

Electrical and Electronic Engineering

Reference14 articles.

1. Fault-tolerant design for VLSI: effect of interconnection requirements on yield improvement of VLSI design;Mangir;IEEE Transactions on Computers,1982

2. Configuration of VLSI array in the presence of defects;Greene;Journal of the ACM (JACM),1984

3. Efficient reconfiguration algorithms for degradable VLSI/WSI arrays;Kuo;IEEE Transactions on CAD of Integrated Circuits and Systems,1992

4. On the reconfiguration of degradable VLSI/WSI arrays;Low;IEEE Transactions on CAD of Integrated Circuits and Systems,1997

5. Reconfiguration algorithms for power efficient VLSI subarrays with four-port switches;Wu;IEEE Transactions on Computers,2006

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