A novel bit-line direct-sense circuit that uses a feedback system for high-speed Flash memory-Reference-Cited by-同舟云学术

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A novel bit-line direct-sense circuit that uses a feedback system for high-speed Flash memory

Published:2006 Issue:8 Volume:89 Page:1-8
ISSN:8756-663X
Container-title:Electronics and Communications in Japan (Part II: Electronics)
language:en
Short-container-title:Electron. Comm. Jpn. Pt. II

Author:

Kadowaki Takuya,Nakamura Hiroki,Sakuraba Hiroshi,Masuoka Fujio

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference5 articles.

1. Design of a sense circuit for low-voltage flash memories

2. A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

3. , , , , , , , , , , , , , . A channel-erasing 1.8 V-only 32Mb NOR flash EEPROM with a bit-line direct-sensing scheme. IEEE Int Solid-State Circuits Conf Dig Tech Papers, p 814– 815, 2000.

4. , , , , , , , , , , , , . Novel 0.44 m2 Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded application. IEDM Tech Dig 1998, p 975– 997.

5. , , , , , , . A novel high-density 5F2 NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories. IEDM Tech Dig, 1997, p 271– 274.

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