Affiliation:
1. Electrical Engineering Department Semnan University Semnan 35131-19111 Iran
Abstract
This work presents a double‐gate junctionless metal‐oxide field‐effect transistor (JLT) in a 20 nm regime by modifying central potential. In the proposed device, the off‐state current is reduced due to modifying the potential in the middle of the channel. The proposed structure is called as a modified central potential junctionless transistor (MCP‐JLT). The suggested device embeds two dielectric pockets (DPs) into the middle of the channel. The proposed technique has several effects on the proposed structure. Also, the impact of the DPs into the channel on the performance device is discussed. The proposed MCP‐JLT structure decreases the off‐state current (IOFF) by three orders of magnitude; besides, it can suppress the lateral electric field and also slightly reduces the drive current (ION), and reduces subthreshold swing (SS) compared to a typical junctionless FET (C‐JLT). Furthermore, the effect of the gate insulator materials on the proposed device's performance is discussed.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Surfaces, Coatings and Films,Surfaces and Interfaces,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Cited by
1 articles.
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