Challenges of Wafer‐Scale Integration of 2D Semiconductors for High‐Performance Transistor Circuits
Author:
Affiliation:
1. Imec kapeldreef 75 Heverlee B7001 Belgium
Publisher
Wiley
Subject
Mechanical Engineering,Mechanics of Materials,General Materials Science
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/adma.202109796
Reference63 articles.
1. Advancing Monolayer 2-D nMOS and pMOS Transistor Integration From Growth to Van Der Waals Interface Engineering for Ultimate CMOS Scaling
2. Graphene and two-dimensional materials for silicon technology
3. Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning
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