A 5-Gbps USB3.0 transmitter and receiver linear equalizer-Reference-Cited by-同舟云学术

A 5-Gbps USB3.0 transmitter and receiver linear equalizer

Published:2014-02-28 Issue:7 Volume:43 Page:900-916
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Terzopoulos Nikolaos¹,Laoudias Costas¹,Plessas Fotis¹,Souliotis George¹,Koutsomitsos Sotiris¹,Birbas Michael¹

Affiliation:

1. Analogies S.A.; Patras Science Park Patras Greece 26504

Funder

Corallia-Greece

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference19 articles.

1. Universal serial bus 3.0 Specification 2011

2. PHY Interface For PCI Express, SATA, and USB 3.0 Architectures 2011 http://www.intel.com/content/www/us/en/io/pci-express/phy-interface-pci-express-sata-usb30-architectures.html

3. USB Super Speed Electrical Compliance Methodology 2009 http://www.usb.org/developers/whitepapers/USB_3_0_e-Compliance_methodology_0p5_whitepaper.pdf

4. Lin M-S et al A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity IEEE Asian Solid-State Circuits Conference 2009 177 180

5. A 6-gbit/s hybrid voltage-mode transmitter with current-mode equalization in 90-nm CMOS;Palermo;IEEE Transactions on Circuits and Systems II,2012

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