A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity-Reference-Cited by-同舟云学术

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A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity

Published:2009-11 Issue: Volume: Page:
ISSN:
Container-title:2009 IEEE Asian Solid-State Circuits Conference
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Author:

Lin Mu-Shan,Tsai Chien-Chun,Chang Chih-Hsien,Peng Yung-Chow,Yu Tsung-Hsin,Chien Jinn-Yeh,Chen W.D.,Lu Chi-Chang,Chen Wei-Chih,Fu Jimmy,Yang S.J.,Chen Chien-Hung,Deng Kuo-Liang,Wen C.H.,Wang L.Y.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5351184/5357143/05357154.pdf?arnumber=5357154

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