A wide range delay locked loop for low power and low jitter applications-Reference-Cited by-同舟云学术

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A wide range delay locked loop for low power and low jitter applications

Published:2017-09-05 Issue:3 Volume:46 Page:401-414
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int J Circ Theor Appl

Author:

Estebsari Motahhareh¹,Gholami Mohammad²^ORCID,Ghahramanpour Mohammad Javad¹

Affiliation:

1. Electrical Engineering Department; Hadaf Institute of Higher Education; Sari Iran

2. Faculty of Engineering and Technology; University of Mazandaran; Babolsar Iran

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers;Gholami;Intern J Circ Theor Appl,2015

2. A wide frequency range delay line for fast-locking and low power delay-locked-loops;Estebsari;Analog Integr Circuits Signal Process,2017

3. Total jitter of delay-locked loops due to four main jitter sources. Very large scale integration (VLSI) systems;Gholami;IEEE Transactions on,2015

4. A 0.6v low power wide range delay locked loop in 0.18 μm CMOS;Lu;IEEE Microwave Wireless Comp Lett,2009

5. Kazeminia S Sofi Mowloodi S Hadidi K Wide-range 16-phases DLL based on improved dead- zone phase detector and reduced gain charge pump 133 138 2014

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1. Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70 μm pixel pitch;Journal of Instrumentation;2024-01-01

2. A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor;Microprocessors and Microsystems;2023-11

3. Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop;Journal of Physics: Conference Series;2023-10-01

4. Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-01

5. A low power and jitter delay cell with pulse width modulation for wide range delay lock loops;Microelectronics Journal;2021-06

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