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Performance of a new split digital phase lock loop in additive wideband Gaussian noise

  • Published:2013-01-25 Issue:12 Volume:27 Page:1107-1117
  • ISSN:0890-6327
  • Container-title:International Journal of Adaptive Control and Signal Processing
  • language:en
  • Short-container-title:Int. J. Adapt. Control Signal Process.

Author:

Sarkar Surjadeep1,Maulik Ujjwal2,Biswas Baidyanath3

Affiliation:

1. Department of Information Technology; Jalpaiguri Government Engineering College; Jalpaigri 735102 West Bengal India

2. Department of Computer Science and Engineering (CSE); Jadavpur University; Kolkata, West Bengal India

3. Education Division; Sir J. C. Bose School of Engineering, SKF Group; Mankundu 712139 West Bengal India

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Signal Processing,Control and Systems Engineering

Reference16 articles.

1. Elimination of truncation and round off error and enhancement of stability using a new split loop DPLL;Sarkar;International Journal of Communication System,2012

2. Performance analysis of the 2nd order PLL when phase modulation added to the VCO;Chaterjee;IETE Journal of Research,2010

3. A novel approach to design split-loop DPLL;Chaterjee;International Journal of Engineering Studies,2010

4. Redusing the PLL noise bandwidth by a digital split-loop;Gustaru;IEEE Communication Letters,1999

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1. Improved Analog Costas Loop with Fuzzy Logic Controller;Studies in Autonomic, Data-driven and Industrial Computing;2024

2. A novel DSP-based PFC-DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity;International Journal of Communication Systems;2014-10-05
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