Effect of gate-length downscaling on the analog/RF and linearity performance of InAs-based nanowire tunnel FET
Author:
Affiliation:
1. ECE Department; Silicon Institute of Technology; Bhubaneswar Odisha India
2. CSE Department; West Bengal University of Technology; Kolkata West Bengal India
3. ECE Department; Kalyani Government Engineering College; Kolkata West Bengal India
Publisher
Wiley
Subject
Electrical and Electronic Engineering,Computer Science Applications,Modelling and Simulation
Reference24 articles.
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4. Performance comparison between p-i-n tunneling transistors and conventional MOSFETs;Koswatta;IEEE Trans Electron Dev,2009
5. Krishnamohan T Kim D Raghunathan S Saraswat K Double-gate strained-Ge heterostructures tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope IEDM Tech. Dig 2008
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1. Comprehensive characterization of a high‐performance double heterojunction InGaAs pHEMT for linear power‐efficient amplifiers applications;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2024-07
2. Band gap and gate metal engineering of novel hetero-material InAs/GaAs-based JLTFET for improved wireless applications;Journal of Materials Science: Materials in Electronics;2021-01-01
3. Investigation of RF and linearity performance of electrode work‐function engineered HDB vertical TFET;Micro & Nano Letters;2019-01
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