P-42: A Novel Gate Driver Circuit Design for Ultra Slim Border
Author:
Affiliation:
1. Advanced Research Center(ARC), AUO corp., Hsinchu Science Park, Taiwan, ROC
Publisher
Wiley
Reference8 articles.
1. Highly reliable integrated gate driver circuit for large TFT-LCD applications;Lin;IEEE Electron Device Lett.,2012
2. Integrated a-Si TFT gate driver with reducing clock duty ratio;Chen;SID Symposium Digest Tech Papers,2009
3. Design of integrated drivers with Amorphous Silicon TFTs for small displays basic concept;Lebrun;SID Symposium Digest Tech Papers,2005
4. Implementation of an a-Si:H TFT gate driver using a five- transistor integrated approach;Liao;IEEE Trans Electron Devices,2012
5. Low power gate driver circuits for narrow bezel panel application;Zheng;SID Symposium Digest Tech Papers,2012
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Clocked control scheme of separating TFTs for a node‐sharing LTPS TFT shift register with large number of outputs;Journal of the Society for Information Display;2020-02-18
2. P-78: A Novel HVA Curing Wires Design Using Switch TFT to Reduce Curing Pads for Gate Driver on Array Liquid Crystal Display;SID Symposium Digest of Technical Papers;2018-05
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