P-4: Integrated a-Si TFT Gate Driver with Reducing Clock Duty Ratio-Reference-Cited by-同舟云学术

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P-4: Integrated a-Si TFT Gate Driver with Reducing Clock Duty Ratio

Published:2009 Issue:1 Volume:40 Page:1092
ISSN:0097-966X
Container-title:SID Symposium Digest of Technical Papers
language:en
Short-container-title:SID Symposium Digest

Author:

Chen Shyh-Feng,Chang Lee-Hsun,Chen Jing-Ru,Lin Shih-Chyn,Yu Chiu-Mei,Hsu Je-Hao,Chen I-Chun

Publisher

Wiley

Reference5 articles.

1. Hyung Nyuck Cho, et al, “a-Si TFT Gate Driver Circuit Having Dual Pull-down Structure with Shared Node Controller”, IDW 2006, pp. 285 – 288.

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