Increasing data reuse of sparse algebra codes on simultaneous multithreading architectures-Reference-Cited by-同舟云学术

Increasing data reuse of sparse algebra codes on simultaneous multithreading architectures

Published:2009-10 Issue:15 Volume:21 Page:1838-1856
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Pichel J. C.,Heras D. B.,Cabaleiro J. C.,Rivera F. F.

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference35 articles.

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2. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading;Lo;ACM Transactions on Computer Systems,1997

3. Tullsen DM, Eggers S, Levy HM. Simultaneous multithreading: Maximizing on-chip parallelism. Proceedings of the 22th Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, 1995; 392-403.

4. Hily S, Seznec A. Standard memory hierarchy does not fit Simultaneous Multithreading. Proceedings of the Workshop on Multithreaded Execution Architecture and Compilation (with HPCA-4), Las Vegas, U.S.A., 1998.

5. A technique for accelerating the convergence of restarted GMRES;Baker;SIAM Journal on Matrix Analysis and Applications,2005

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