A hardware counter-based toolkit for the analysis of memory accesses in SMPs-Reference-Cited by-同舟云学术

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A hardware counter-based toolkit for the analysis of memory accesses in SMPs

Published:2013-08-14 Issue:6 Volume:26 Page:1328-1341
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Lorenzo Oscar G.¹,Pena Tomás F.¹,Cabaleiro José C.¹,Pichel Juan C.¹,Lorenzo Juan A.¹,Rivera Francisco F.¹

Affiliation:

1. Centro de Investigación en Tecnoloxías da Información (CITIUS); University of Santiago de Compostela; Santiago de Compostela Spain

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cpe.3122/fullpdf

Reference32 articles.

1. Precise Event-Based Sampling (PEBS) http://perfmon2.sourceforge.net/pfmon_intel_core.html#pebs

2. Lorenzo OG Lorenzo JA Cabaleiro JC Heras DB Suarez M Pichel JC A study of memory access patterns in irregular parallel codes using hardware counter-based tools International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA) 2011 920 923

3. Review of Performance Analysis Tools for MPI Parallel Programs

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multicore cache hierarchies: design and programmability issues;Concurrency and Computation: Practice and Experience;2013-12-10

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