Improving TLB performance on current chip multiprocessor architectures through demand-driven superpaging
Author:
Affiliation:
1. Department of Computer Science; Texas State University; San Marcos; TX; USA
Publisher
Wiley
Subject
Software
Link
http://onlinelibrary.wiley.com/wol1/doi/10.1002/spe.2128/fullpdf
Reference31 articles.
1. Marin G Mellor-Crummey J Pinpointing and exploiting opportunities for enhancing data reuse In Proceedings of the 2008 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'08) 2008
2. Bhattacharjee A Martonosi M Characterizing the TLB behavior of emerging parallel workloads on chip multiprocessors Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, 2009
3. McCurdy C Cox AL Vetter J Investigating the TLB behavior of high-end scientific applications on commodity microprocessors Proceedings of the ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and Software 2008
4. Supporting superpage allocation without additional hardware support
5. Scott Schneider CDA Nikolopoulos DS Scalable locality-conscious multithreaded memor allocation In Proceedings of International Symposium on Memory Management 2006
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