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Investigating memory prefetcher performance over parallel applications: From real to simulated

  • Published:2021-01-28 Issue:18 Volume:33 Page:
  • ISSN:1532-0626
  • Container-title:Concurrency and Computation: Practice and Experience
  • language:en
  • Short-container-title:Concurrency Computat Pract Exper

Author:

Girelli Valéria S.1ORCID,Moreira Francis B.1ORCID,Serpa Matheus S.1ORCID,Carastan‐Santos Danilo1ORCID,Navaux Philippe O. A.1ORCID

Affiliation:

1. Informatics Institute Federal University of Rio Grande do Sul – UFRGS Porto Alegre Brazil

Funder

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul

Petrobras

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference47 articles.

1. Hitting the memory wall: implications of the obvious;Wulf W;Comput Archit News,1996

2. Challenges in computer architecture evaluation

3. Impacto do Prefetcher na Precisão de Simulações de Arquiteturas Paralelas

4. ZSim

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mitigating execution unit contention in parallel applications using instruction‐aware mapping;Concurrency and Computation: Practice and Experience;2021-12-30

2. Computer architecture and high performance computing;Concurrency and Computation: Practice and Experience;2021-07-28

3. Investigating memory prefetcher performance over parallel applications: From real to simulated;Concurrency and Computation: Practice and Experience;2021-01-28
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