LWMPI: An MPI library for NoC‐based lightweight manycore processors with on‐chip memory constraints-Reference-Cited by-同舟云学术

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LWMPI: An MPI library for NoC‐based lightweight manycore processors with on‐chip memory constraints

Published:2021-11-08 Issue: Volume: Page:
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat Pract Exper

Author:

Fellipe Uller João¹,Vicente Souto João¹,Henrique Penna Pedro²³,Castro Márcio¹^ORCID,Freitas Henrique²^ORCID,Méhaut Jean‐François³

Affiliation:

1. Laboratório de Pesquisa em Sistemas Distribuídos (LaPeSD) Universidade Federal de Santa Catarina (UFSC) Floríanópolis Brazil

2. Computer Architecture and Parallel Processing Team (CArT) Pontifícia Universidade Católica de Minas Gerais (PUC Minas) Belo Horizonte Brazil

3. Laboratoire d'Informatique de Grenoble (LIG) Université Grenoble Alpes (UGA) Saint‐Martin‐d'Hères France

Funder

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.6693

Reference29 articles.

1. On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms;Francesquini E;J Parallel Distrib Comput (JPDC),2015

2. Energy‐efficient near‐threshold parallel computing: the PULPv2 cluster;Rossi D;IEEE Micro,2017

3. MelpignanoD BeniniL FlamandE et al.Platform 2012 a many‐core computing accelerator for embedded SoCs. Proceedings of the Design Automation Conference (DAC); 2012:1137‐1142; ACM Press New York NY

4. The celerity open‐source 511‐core RISC‐V tiered accelerator fabric: fast architectures and design methodologies for fast chips;Davidson S;IEEE Micro,2018

5. deDinechinBD AyrignacR BeaucampsPE et al.A clustered manycore processor architecture for embedded and accelerated applications. Proceedings of the IEEE High Performance Extreme Computing Conference (HPEC); 2013:1‐6; Waltham.

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